DESIGN AND IMPLEMENTATION OF ACCURATE HYBRID KS WITH CS ADDER FOR HIGH SPEED OPERATIONS

Abstract

In complex data processing, the basic elements which are known as adders are used for efficient VLSI design. For high speed design processor the CS (Carry Select) adder circuit is used. In CMOS technology, by preserving the circuit speed there is a scope for decreasing the design area and power. The architecture of CS adder is such that it is of high speed, efficient area, and less power dissipation. In a number of computer systems the Carry Select Adder (CSA) is used by producing numerous carry bits to reduce the impact of carry propagation delay and for the required output picking a carry. In integrated circuits one of the most important design objectives is known as power dissipation, after area & speed. In such circuits the most widely used components are known as adders, for researchers the efficient adder design is much concern. In this work, for high speed operations the CS adder with accurate hybrid KS (Kogge Stone) implementation and design was presented. To obtain higher speed hybrid CSA design was presented in this work, which utilizes both Carry Look ahead Adder (CLA) and Kogge Stone adders advantages. A particular type of adder is known as Kogge stone adder and hence, due to faster carry generation one of the high speed addition method was regarded widely. In the modified adders initial stage, the look ahead adder was employed to boost its speed, if the number of bits are less then its computation performance is better.