Short channel effects and other parameter modifications have a significant influence on semiconductor devices at nanoscale technology nodes. To ensure sufficient manufacturing yield while balancing power, area, and resilience, a creative and comprehensive circuit-level technique is needed. A different approach to bulk devices for lowering leakage power and short channel effects is FinFET-based design. Numerous strategies were previously used to reduce leakage power, but they were only able to do so to a limited extent. I've developed a hybrid method and applied it to a 6T SRAM cell with a FinFET foundation. Because leakage current is reduced and there is no area penalty, it lowers power dissipation in standby mode. At a fixed 45 nm channel length on Cadence Virtuoso at room temperature, we achieved a decrease in leakage current and static power dissipation at 25.59% and 31.29%, respectively, compared to the standard FinFET.