The primary cause of the total device capacitance in nanoscale FETs is progressively turning out to be the parasitic capacitance, which lowers the performance of the device and circuit. The use of multi-gate FETs, including FinFET and gate-all-around FETs, exacerbates this problem. Corner spacers are a concept for gate-all- around nanowire field-effect transistors that minimize ON-current degradation while significantly reducing parasitic capacitance. We show that, compared to the device equipped with full nitride spacers, the parasitic capacitance of a precisely designed corner spacer in a nanowire FET may be reduced by more than 80%. When compared to the full spacer, the corner spacer design in the circular oscillator stage has a delay and energy usage that are less than 40% of the latter.- 5.This work shows how manufactured spacers can be used to improve performance and allow for additional scaling.