This paper presents and employs TCAD modeling to demonstrate a source/drain configuration for nanowire FETs, including an extended doping profile, spacer dielectric constant, and spacer width. The results indicate that, although having a relatively large nanowire diameter, asymmetric graded lightly doped drains (AGLDD) provide excellent control over short channel effects (SCE) and have strong driving capabilities. By using high-k spacer material and changing the width of the drain spacer, it is possible to achieve desirable SCE immunity and increase the overdrive current, while ensuring that the parasitic capacitance remains within an acceptable range. This proposal provides a practical framework for developing low power nanowire FETs in the future