A multiplication algorithm known as the Modified Vedic Multiplier is a multiplication algorithm that makes use of a unique way that mixes crosswise and vertical calculations. This algorithm was inspired by the notions of ancient Vedic mathematics. The Modified HSCG-SCG Adder is an improved form of traditional binary adders that computes the final result using a carry tree and generates partial products using a decoder. This work provides the Modified HSCG-SCG Adder. The combination of the Modified Vedic Multiplier and the Modified HSCG-SCG Adder offers a number of advantages in comparison to conventional methods of multiplication. These advantages include a reduction in latency, a reduction in power usage, and a speedier processing speed. In particular, applications that require high-speed multiplication, such as encryption, digital signal processing, and image processing, are particularly well-suited for this combination. A technique that enables testing and simulation with hardware simulators such as VIVADO is constructed with the help of Verilog Hardware Description Language (HDL), which is employed in its construction.