This paper presents the analysis and design of an active element-based class-J Power Amplifier (PA). A proper PA needs to be designed to achieve the required power output over a bandwidth (BW) that supports the emerging 5G applications without sacrificing linearity. Among different PAs, class-J mode PA will be more suitable for linear and broadband applications. Therefore, a class-J PA design that operates at 5GHz (i.e., sub-6GHz 5G frequency band) with an active element-based approach using Silterra 130nm CMOS process technology to estimate its feasibility for integration without compromising on the performance is described in this paper. The simulation results show that the saturated power output (Psat) of 27dBm with a maximum value of 13.73dB power gain and power output at 1dB compression point (P1dB) of 26.2dBm are obtained with a BW of approximately 500 MHz by supplying the PA with 5V to deliver into 50 Ω load. The PA’s layout with the estimated chip size of (13.8X20.0) um2 reveals its feasibility for the integration.