This paper presents a complete review of SRAM cells employing tunnel field-effect transistors ( TFE Ts) at the nanoscale. The research focuses on the development and testing of a novel PFAS-based, high-performance SRAM cell designed for nanoscale applications in nanotechnology. Key performance measures such as static noise margin (SNM) read and write access times, power consumption, stability, and data retention are all assessed. The proposed PFAS-based SRAM cell combines sophisticated FET transistors with optimized cell layouts to improve area efficiency and performance. Power gating and adaptive body biasing are used to increase energy efficiency while maintaining stability and dependability. The PFAS-based SRAM cell has excellent stability and data retention, making it ideal for ultralow-power, high-performance applications in nanoscale electronic systems. This study examines SRAM cell evaluation at nanotechnology using tunnel FETs. To summarize, tunnel FETs, or TFETs for short, are semiconductors with all the characteristics required to function as transistors in circuits with stringent specifications, such as those found in the Internet of Things (IoT) and biomedical applications. Specifically, the Gate-All-Around (GAA) FET device architecture provides better gate junction control throughout the channel and an improved ION/IOFF ratio. The main goal of this work is to determine whether using the GANTLET circuit architecture to build dependable, low-power SRAM memory cells is feasible.